Analog to digital converters (ADC) convert a continuous analog signal, for example, a continuous analog voltage, to a digital equivalent that represents the magnitude or amplitude of the analog voltage. In general, the ADC samples the analog signal at discrete time periods and converts each sample into a corresponding digital value. The resulting sampling rate affects the type of circuit used for the ADC. Conventional ADC circuit arrangements, in order of increasing sampling rate, include successive approximation (SAR) ADC, pipeline ADC and flash ADC. Since the SAR ADC uses only one comparator, this ADC has low power consumption. However, for an n-bit SAR ADC, n clock cycles are required. Therefore, the SAR ADC suffers from low speed. At the other end of the sampling rate is flash ADC. While flash ADC provides high speed, it requires a large number of comparators equal to 2n−1 where n is the ADC bit resolution. The result is a large area and high power consumption.
A conventional pipeline ADC utilizes a smaller number of comparators than flash ADC and has a higher throughput than SAR ADC as a result of the pipelining architecture. However, pipeline ADC suffers from a speed limitation due to the need for a high-gain/linearity amplifier that is used to amplify the residue. One proposed modification to these conventional ADCs is a sub-ranging ADC. The sub-ranging ADC also has a smaller number of comparators than a flash ADC and provides a higher speed than the pipeline ADC. The sub-ranging provides for two separate conversions, a coarse conversion and a fine conversion. This architecture, however, imposes a speed limitation, as these two separate conversions need to be accomplished, i.e., there is no pipelining. In order to achieve the same output, the sub-ranging ADC is clocked at twice the speed.